A programmable logic switch is an element which controls on/off of a logic switch (for example, a transistor or the like) in accordance with data retained in a memory. In general, the programmable logic switch is used in programmable logic devices such as an FPGA (Field Programmable Gate Array) or the like in which a logic operational circuit or an interconnection circuit needs to be reconfigured. For example, such programmable logic device includes plural wirings and a connection unit (plural connection units) for switching connection/disconnection of these wirings. The programmable logic switches may be used in such connection unit.
In a programmable logic switch used in the FPGA, a volatile memory such as an SRAM is used as a memory. If the power supply is turned off, therefore, data stored in the memory is lost. Therefore, there is a problem that data must be read anew from a memory region provided separately when the power supply is turned on again. Furthermore, in general, the SRAM is formed of six transistors. Therefore, there is a problem that the area of the chip becomes large in an FPGA which uses a large number of SRAMs.
Schemes using a nonvolatile flash memory as a memory in the programmable logic switch are known. In one of the schemes, one cell in the programmable logic switch is formed of two nonvolatile memory transistors and one switching transistor (pass transistor). As the memory transistors, for example, flash memory transistors are used. A power supply voltage or 0 V is input to the switching transistor at its gate via one of the two flash memory transistors. When it is desired to write data into the memory, a write voltage is applied to a flash memory transistor at its gate. In general, the write voltage is approximately 20 V. At this time, 0 V is applied to the memory transistor at its source. The writing utilizes the principle called FN (Fowler-Nordheim) tunnel current, and the writing is said to be advantageous in shrinking the sizes of the memory transistors. In the case where the programmable logic switch is disposed in an array form, a plurality of memory transistors share a gate. For implementing selective writing, a write inhibit voltage must be applied to a source of a memory transistor in an unselected cell. At this time, a conductive channel is formed in the memory transistor in the unselected cell, and the write inhibit voltage is unwillingly applied to a gate of the memory transistor in the unselected cell. In general, approximately 5 V is needed as the write inhibit voltage. On the other hand, it is desirable to make a gate insulation film of the switching transistor as thin as approximately several nm in order to obtain high driving force. Therefore, there is a fear that the gate insulation film might be broken down by the write inhibit voltage. If the gate insulation film of the switching transistor is made sufficiently thick, it is possible to prevent breakdown caused by the write inhibit voltage. However, the driving force of the switching transistor gets small and the speed of the programmable logic switch falls.
In another one of the schemes using a nonvolatile flash memory as a memory in the programmable logic switch, one cell in the programmable logic switch is formed of two nonvolatile memory transistors, one switching transistor, and one access transistor. As the memory transistors, for example, flash memory transistors are used. A power supply voltage or 0 V is input to the switching transistor at its gate via one of the two flash memory transistors. The two memory transistors in the same cell share a gate electrode. When it is desired to write data into one of the two memory transistors, a first write voltage is applied to the common gate of the memory transistors and a second write voltage is applied to a memory transistor into which data is to be written, at its source. At this time, 0 V is applied to the gate of the switching transistor via the access transistor. As a result, the second write voltage is applied between the source and drain of the memory transistor into which data is to be written. Accordingly, selective writing is implemented. In this scheme, hot-electrons are used for writing into the memory transistor. In other words, hot-electrons generated by a potential difference between the source and drain are implanted into a charge trap film by the voltage applied to the gate. However, it is known that in general the generation efficiency of hot-electrons falls if the gate length of a transistor becomes smaller than 100 nm. Therefore, the write scheme using hot-electrons becomes difficult because of the size shrinking of transistors. In order to implement the writing, therefore, the ion implantation condition and the like for the memory transistors must be restricted strictly. As a result, the development cost therefor and a cost for holding down variations to low values increases.